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| STE400P 10/100 FAST ETHERNET 4 PORT TRANSCEIVER 1 GENERAL DESCRIPTION The STE400P, also referred to as STEPHY4, is a high performance Fast Ethernet physical layer interface for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for 100BASETX of IEEE802.3u and 10BASE-T of IEEE802.3. The STE400P supports both half-duplex and full-duplex operation, at 10 and 100 Mbps operation. Its operating mode can be set using auto-negotiation, parallel detection or manual control. It also allows for the support of auto-negotiation functions for speed and duplex detection. 2 FEATURES PQFP208 ORDERING NUMBER: STE400P 10BASE-T compliant s s Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX MII interface Standard CSMA/CD or full duplex supported 2.1 INDUSTRY STANDARD s s s IEEE802.3u 100BASE-TX and IEEE802.3 Figure 1. BLOCK DIAGRAM FOR 1 PORT LEDS LEDS 100Mb/s TX_CLK TXD[3:0] TX_ER TX_EN Serial Management TX Channel Scrambler Parallel to Serial NRZ To NRZI Encoder Binary To MLT3 Encoder TRANSMITTER 10/100 10 TX Filter TXP TXN 4B/5B 10Mb/s NRZ To Manchester Encoder Link Pulse Generator MDIO Interface / Controller MDC REGISTERS Auto Negotiation Loopback Clock Generation System Clock RXD[3:0] RX_ER RX_DV RX_CLK MII RX Channel 100Mb/s 4B/5B Descrambler Code Align Binary To MLT3 Decoder Adaptive Equalization BaseLine Wander Serial to Parallel NRZI To NRZ Decoder Clock Recovery COL CRS HW configuration pins RECEIVER 10/100 RXP RXN 10Mb/s HW Config Power Down NRZ To Manchester Encoder Link Pulse Detector 10 TX Filter Clock Recovery SMART Squelch November 2002 This is preliminary information on a new product now in development. Details are subject to change without notice. Version: A11 1/36 www..com STE400P Table of Contents 1 2 GENERAL DESCRIPTION................................................................................................................. 1 FEATURES ........................................................................................................................................1 2.1 Industry standard .....................................................................................................................1 2.2 Physical Layer..........................................................................................................................3 2.3 LED Display ............................................................................................................................. 3 System Diagram of the STE400P Application....................................................................................3 Pin Assignment Diagram ...................................................................................................................4 Operational description ....................................................................................................................10 5.1 Resetting the STE400P..........................................................................................................10 5.2 Isolate Mode...........................................................................................................................10 5.3 Loopback Mode......................................................................................................................10 5.4 Full Duplex Mode ...................................................................................................................10 5.5 100BASE-T MODE ................................................................................................................10 Registers and Descriptors Description .............................................................................................10 6.1 MII Management Interface .....................................................................................................11 6.2 Register List ...........................................................................................................................11 6.3 Register Descriptions .............................................................................................................12 Device Operation..............................................................................................................................21 7.1 100BASE-TX Transmit Operation ..........................................................................................21 7.2 100BASE-TX Receiving Operation ........................................................................................22 7.3 10BASE-T Transmission Operation .......................................................................................22 7.4 10BASE-T Receive Operation ...............................................................................................22 7.5 Loop-back Operation..............................................................................................................22 7.6 Full Duplex and Half Duplex Operation..................................................................................23 7.7 Auto-Negotiation Operation....................................................................................................23 7.8 Power Down Operation ..........................................................................................................23 7.9 LED Display Operation...........................................................................................................23 7.10 Reset Operation .....................................................................................................................23 7.11 Preamble Suppression ...........................................................................................................24 7.12 Remote Fault..........................................................................................................................24 7.13 Transmit Isolation...................................................................................................................24 Electrical Specifications and Timings ...............................................................................................25 3 4 5 6 7 8 2/36 STE400P 2.2 PHYSICAL LAYER s s s s s s s s s Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T Provides Full-duplex operation on both 100Mbps and 10Mbps modes Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for Base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides loop-back modes for diagnostic Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder Supports external transmit transformer with turn ratio 1.41:1 Supports external receive transformer with turn ratio 1:1 2.3 LED DISPLAY s s s s s s s Provides 2 kinds of LED display mode: First mode - 3 LED displays for 100Mbps(on) or 10Mbps(off) Link(Keeps on when link ok) or Activity(Blink with 10Hz when receiving or transmitting but not collision) FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding) Second mode - 4 LED displays for 100 Link(On when 100M link or 10 Link(On when 10M link ok Activity (Blink with 10Hz when receiving or transmitting) FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding) SYSTEM DIAGRAM OF THE STE400P APPLICATION 3 QUAD ETHERNET MAC CONTROLLER STE400P 4 PORT 10/100MBPS PHY MAGNETICS MAGNETICS MAGNETICS MAGNETICS RJ45 RJ45 RJ45 RJ45 3/36 STE400P 4 PIN ASSIGNMENT DIAGRAM 4/36 STE400P Table 1. Pin Description Pin. MII Interface 33 34 35 36 208 1 9 10 150 149 148 147 124 123 122 121 37 11 146 120 27 12 145 130 19 20 21 23 192 193 194 195 170 169 168 167 138 137 136 134 24 196 166 133 18 191 171 139 TXD3 TXD2 TXD1 TXD0 TXD3 TXD2 TXD1 TXD0 TXD3 TXD2 TXD1 TXD0 TXD3 TXD2 TXD1 TXD0 {1} {1} {1} {1} {2} {2} {2} {2} {3} {3} {3} {3} {4} {4} {4} {4} Ipd Transmit Data. The Media Access Controller (MAC) drives data to the STE400P using these inputs. These signals must be synchronized to the TX-CLK. Name Type Description TXEN1 TXEN2 TXEN3 TXEN4 TXC1 TXC2 TXC3 TXC4 RXD3 RXD2 RXD1 RXD0 RXD3 RXD2 RXD1 RXD0 RXD3 RXD2 RXD1 RXD0 RXD3 RXD2 RXD1 RXD0 {1} {1} {1} {1} {2} {2} {2} {2} {3} {3} {3} {3} {4} {4} {4} {4} Ipd Transmit Enable. The MAC asserts this signal when it drives valid data on the TXD inputs. This signal must be synchronized to the TX-CLK. O3s Transmit Clock. Normally the STE400P drives TX-CLK. Refer to the Clock Requirements discussion in the Functional Description section. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. Receive Data. The STE400P drives received data on these outputs, synchronous to RX-CLK. RXD4 is driven only in Symbol (5B) Mode. O3s RXDV1 RXDV2 RXDV3 RXDV4 RXER1 RXER2 RXER3 RXER4 O3s Receive Data Valid. The STE400P asserts This signal when it drives valid data on RXD. This output is synchronous to RX-CLK. O3s Receive Error. The STE400P asserts this output when it receives invalid symbols from the network. This signal is synchronous to RX-CLK. In Symbol (5B) Mode this pin is also equivalent to RXD4. 5/36 STE400P Table 1. Pin Description Pin. 17 190 172 140 25 205 151 132 26 206 157 131 117 118 119 Clock 6 CLK25 I Reference clock input. - 25 MHz This pin must be driven with a continuous 25 MHz clock. Name RXC1 RXC2 RXC3 RXC4 COL1 COL2 COL3 COL4 CRS1 CRS2 CRS3 CRS4 MDC MDIO RESET# Type O3s Description Receive Clock. This continuous clock provides reference for RXD. RXDV, and RXER signals. Refer to the Clock Requirements discussion in the Functional Description section. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. Collision Detected. The STE400P asserts this output when detecting a collision. This output remains High for the duration of the collision. This signal is asynchronous and inactive during full-duplex operation. Carrier Sense. During half-duplex operation (PR0:8=0), the STE400P asserts this output when either transmit or receive medium is non idle. During full duplex operation (PR0:8=1), CRS is asserted only when the receive medium is non-idle. Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 2.5 MHz. Management Data Input/Output, Bi-directional serial data channel for PHY communication. Reset: Active low. Resets the STE400P. Pin not included in NAND I/O pd O3s Ipd I/O Ipu Media Connections 65 66 70 69 87 88 92 91 60 61 75 74 82 83 97 96 LED 203 184 178 159 LNKLED# {1} LNKLED# {2} Ser SFRM# LNKLED# {3} LC_SER_LED_EN LNKLED# {4} SER_LED_EN# O Link Integrity LED: Active low. This output signal indicates the link status of the PHY. LNKLED is driven low when the link to the PHY is good. Serial LED mode is enabled by "pull-down" of pin 159 during reset. WHen the Serial LED mode is enabled, pin 184 becomes the Serial LED mode frame signal. Low cost serial LED mode is enabled by "pull down" of pin 198 during reset.. TD+ {1} TD- {1} TD+ {2} TD- {2} TD+ {3} TD- {3} TD+ {4} TD- {4} RD+ {1} RD- {1} RD+ {2} RD- {2} RD+ {3} RD- {3} RD+ {4} RD- {4} Oa Transmit Pair: Differential data is transmitted to the media on the TD+signal pair Ia Receive Pair: Differential data from the media is received on the RD+- signal pair 6/36 STE400P Table 1. Pin Description Pin. 204 185 177 158 202 Name SP100LED# {1} SP100LED# {2} SP100LED# {3} SP100LED# {4} XMTLED#{1} INTR# {1} FDXLED# {1} XMTLED#{2} INTR# {2} FDXLED# {2} Ser SDO# XMTLED#{3} INTR# {3} FDXLED# {3} XMTLED#{4} INTR# {4} FDXLED# {4} RCVLED#{1} ACTLED {1} LC Ser SCLK# RCVLED# {2} ACTLED# {2} Ser SCLK# {2} RCVLED# {3} ACTLED# {3} LC Ser SDO# RCVLED# {4} ACTLED# {4} Transmit Activity LED: Active low output. The transmit activity LED is driven low for approximately 80ms each time there is transmit activity while in the link pass state. When INTR mode is enable, the pin becomes an interrupt output. When FDX LED mode is enabled, the pin becomes FDXLED output. When the Serial LED mode is enabled, pin 183 becomes the Serial LED mode data output signal. Type O Speed 100 LED: Driven low when operating in 100BASE-X modes and high when operating in 10BASE-T modes Description 183 Ood 179 160 201 182 Ood 180 161 MODE 42 Receive Activity LED: Active low output. The receive activity LED is driven low for approximately 80ms each time there is receive activity while in the link pass state. When in either INTR or FDXLED modes, this pin becomes ACTLED output for either receive or transmit activity. When the Serial LED mode is enabled, pin 182 becomes the Serial LED mode clock signal. When the low cost serial LED mode is enabled, pin 201 becomes Low cost serial LED mode clock signal and pin 180 becomes the data output signal. FDXEN Ipd Full-Duplex Enable. When A/N is enabled, FDE determines full-duplex advertisement capability in combination with CFG0 and CFG1. (See Table 2) When A/N is disabled, FDE directly affects full-duplex operation and determines the value of PR0 bit 8 (Full/Half Duplex Mode Select). 38 39 40 104 PHYAD4 PHYAD3 PHYAD2 F100 Ipd PHY Address Selects: These inputs set the three MSB's for the MII management PHY addresses. THe two LSB's, PHYAD1, PHYAD0 are internally wired to each of the four ports: PHYAD[00] = Port1,.., PHYAD[11] = Port4. Force 100BASE-X Operation: When F100 is high and ANEN is low, all transceivers will be forced to 100BASE-X operation. When F100 is low and ANEN is low, all transceivers are forced to 10BASE-T operation. When ANEN is high, F100 has no effect on operation Auto Negotiation Enable: When pulled high, Auto-Negotiation begins immediately after reset. When low, it is disabled after reset. Ipu 105 ANEN Ipu 7/36 STE400P Table 1. Pin Description Pin. 116 115 43 Name ER1 ER0 TESTEN Type Ipu Ipd Description Transmit DAC Edge Rate Control: These pins control the slew rate of each of the transmit DAC's. Test Enable: Active-high test control inputs used along with NANDMD1, 0 and PHYAD[4:2] to select the NAND-chain test mode. Both inputs must be driven high during latching of test mode. Must be pulled low or left unconnected during normal operation. NAND Mode: Active-high test control inputs used along with TESTEN and PHYAD[4:2} to select the NAND-chain test mode. Both inputs must be driven high during latching of the test mode. Must be kept at low or left unconnected during normal operation. Bidirectional pad : input - clk_20lbk used to bypass internal 20 MHz PLL, output - intr as per interrupt register. 54 53 NANDMD1 NANDMD0 Ipd 125 BIAS 78 79 INTR/clk_20lbk I/Opd RDAC VREF B B DAC Bias Resistor: A 5K ohm + - 1% resistor must be connected between this pin and AGND for normal operation. Voltage Reference: Low-impedance bias pin driven by the internal bandgap voltage reference. This pin must be left unconnected during normal operation. JTAG 99 100 101 TMS 102 103 TRST# Ipu Ipu TDI TDO Ipu O3s Test Data Input: Serial data input to the JTAG TAP controller. Sampled on the rising edge of TCK. If unused, may be left unconnected Test Data Output: Serial data output from the JTAG TAP controller. Updated on the falling edge of TCK. Actively driven both high and low when enabled. Test Mode Select: Single control input to the JTAG TAP Controller used to traverse the test-logic state machine. Sampled on the rising edge of TCK. If unused, may be left unconnected Test Clock: Clock input used to synchronize JTAG control and data transfers. If unused, may be left unconnected Test Reset: Asynchronous active-low reset input to the JTAG TAP controller. Must be held low during power up to insure the TAP controller initializes to the test-logic-reset state. May be pulled low continuously when JTAG functions are not used DLL Bypass Test Enable: This pin is for factory test only and must be connected to DVDD or left floating TCK Ipu 44 Power 181 DLLTEST Ipu IVDD 7 8 77 PLLVDD PLLGND BIASVDD Input VDD: +5.0V or +3.3V. If any of the inputs are driven to 5.0V, this pin must be connected to the 5.0V supply. If none of the inputs are driven above 3.3V, this pin may be connected to the 3.3V supply Phase Locked Loop VDD Phase Locked Loop GND Bias VDD 8/36 STE400P Table 1. Pin Description Pin. 80 63 72 85 94 62, 64 67 68 71 73 84 86 89 90 93 95 175 198 176 197 13 129 144 162 173 200 3 14 22 29 50 107 128 135 143 154 163 174 188 199 Name BIASGND Type Bias GND Analog VDD Description AVDD AGND Analog GND DVDD DGND Digital Core VDD Digital Core GND Digital Periphery (Output Buffer) VDD OVDD Digital Periphery (Output Buffer) GND OGND Note: #=active low, I=digital input, O=digital output, I/O=bidirectional, Ia=analog input, Oa=analog output, Ipu=digital input w/ internal pull-up, Ipd=digital input w/ internal pull-down, Ood=open-drain input, O3s=three-state output, I/Opd=bidirectional w/ internal pull-down, B=bias. 9/36 STE400P 5 OPERATIONAL DESCRIPTION 5.1 RESETTING THE STE400P There are two ways to reset each transceiver in the STE400P. A hardware reset pin has been provided which resets all internal nodes inside the chip to a known state. The reset pulse must be asserted for at least 400 ns. Hardware reset should always be applied to a STE400P after power-up. Each transceiver also has an individual software reset capability. To perform software reset, a "1' must be written to bit 15 of the transceiver's MII Control Register. This bit is self-clearing, i.e. that a second write operation is not necessary to end the reset. There is no effect if a "0" is written to the MII Control Register reset bit. 5.2 ISOLATE MODE Each transceiver in the STE400P may be isolated from the MII. When a transceiver is put into isolate mode, all MII inputs are ignored, and all MII outputs are set at high impedance. Only the MII management pins operate normally. Upon resetting the chip, the isolate mode is off. Writing a "1" to bit 10 of the MII Control Register puts the transceiver into isolate mode. Writing a "0" to the same bit removes it from isolate mode. 5.3 LOOPBACK MODE The loopback mode allows in-circuit testing of the STE400P chip. All packets sent in through the TXD pins are looped-back internally to the RXD pins, and are not sent out to the cable. Incoming packets on the cable are ignored. Because of this, the COL pin will normally not be activated during loopback mode. In order to test that the COL pin is actually working, the STE400P may be placed into collision test mode. This mode is enabled by writing a "1" to bit 7 of the MII Control Register. Asserting TXEN will cause the COL output to go high and deasserting TXEn will cause the COL output to go low. The loopback mode may be entered by writing a "1" to bit 14 of the MII Control Register. In order to resume normal operation, bit 14 of the MII Control Register must be "0". Several function bypass modes are also supported which can provide a number of different combinations of feedback paths during loopback testing. These bypass modes include: bypass scrambler, bypass MLT3 encoder and bypass 4B5B encoder. 5.4 FULL DUPLEX MODE The STE400P supports full duplex operation. While in full-duplex mode, a transceiver may simultaneously transmit and receive packets on the cable. The COL signal is never activated while in full-duplex mode. By default, each transceiver in the STE400P powers up in half-duplex mode. When Auto Negotiation is disabled, full duplex operation can be enabled either by a pin (FDXEN) or by an MII register bit (Register "0" bit 8). When Auto Negotiation is enabled in DTE mode, full-duplex capability is advertised by default but can be overridden by a write to the Auto-Negotiation Advertisement Register (04h). 5.5 100BASE-T MODE The same magnetics module is used to interface the twisted-pair cable in 10BASE-T mode and in 100BASETX mode. The data will be two-level Manchester coded instead of three level MLT3 and no scrambling/descrambling or 4B5B coding is performed. Data and clock rates are decreased by a factor of 10, with the NII interface operating at 2.5 MHz. Each transceiver in the STE400P will have a unique PHY address for MII management. THe addresses will be set through the PHY address pins. The pins are latched at the trailing end of reset. Transceiver 1 will have the address AAA00 where AAA=PHYAD4, PHYAD3, PHYAD2. Transceivers 2 - 4 will have addresses AAA01, AAA10 and AAA11, respectively. 6 REGISTERS AND DESCRIPTORS DESCRIPTION 10/36 STE400P There are 20 registers with 16 bits each supported for each port of the STE400P. This includes 9 basic registers which are defined according to the clause 22 "Reconciliation Sub-layer and Media Independent Interface" and clause 28 "Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair" of IEEE802.3u standard. In addition, there are 11 registers for advanced chip control and status information. 6.1 MII MANAGEMENT INTERFACE The STE400P is fully compliant with the IEEE 802.3u MII specifications. 6.2 REGISTER LIST Table 2. Register List Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 10h 11h 12h 13h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh Reg. Index PR0 PR1 PR2 PR3 PR4 PR5 RP6 PR7 PR8 PR9 PR10 PR11 PR12 PR13 PR14 PR15 PR16 PR17 PR18 PR19 Name Control Status PID HI PID LO ANA ANLPA ANE MII Control Register MII Status Register PHY Identifier (HI) Register PHY Identifier (LO) Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Register Descriptions NEXT PAGE Auto-Negotiation Next Page Transmit Register LP NXT PG Auto-Negotiation Link Partner Next Page Transmit Register 100AUXCTL 100BaseX Auxiliary Control Register 100AUX SR 100 RX EC 100 FCSC AUX CSR AUX SSR INT AUX M2 AUX EGSR AUX MODE AUX MPR 100BaseX Auxiliary Status Register 100BaseX Receiver Error Counter 100BaseX False Carrier Sense Counter Auxiliary Control/Status Register AuxiliaryStatus Summary Register Interrupt Register Auxiliary Mode 2 Register Auxiliary Error and General Status Register Auxiliary Mode Register Auxiliary Multiple PHY Register 11/36 STE400P 6.3 REGISTER DESCRIPTIONS Table 3. Register Descriptions Bit # Name Descriptions Default Val RW Type PR0, MII Control Register. The default values on power-up/reset are as listed below. 15 XRST Reset control. 1: Device will be reset. This bit will be cleared by STE400P itself after the reset is completed. Loop-back mode select. 1: Loop-back mode is selected. Network Speed select. This bit's selection will be ignored if Auto-Negotiation is enabled(bit 12 of PR0 = 1). 1:100Mbps is selected. 0:10Mbps is selected. Auto-Negotiation ability control. 1: Auto-Negotiation function is enabled. 0: Auto-Negotiation is disabled. Power-down mode control. 1: Power-down mode is selected. Setting this bit puts the STE400P into power-down mode. During the power-down mode, TXP/TXN and all LED outputs are 3-stated, and the MII interface is isolated. 0 - Normal operation. 1 - Isolate PHY from MII. Setting this control bit isolates the STE400P from the MII, with the exception of the serial management inter-face. When this bit is asserted, the STE400Pdoes not respond to TXD[3:0], TX-EN, and TX-ER inputs, and it presents a high impedance on its TX-CLK, RX-CLK, RX-DV, RX-ER, D[3:0], COL, and CRS outputs. This bit is initialized to 0 unless the configuration pins for the PHY address are set to 00000h during power-up or reset. Re-Start Auto-Negotiation process control. 1: Auto-Negotiation process will be re-started. This bit will be cleared by STE400P itself after the Auto-negotiation restarted. Full/Half duplex mode select. 1: full duplex mode is selected. This bit will be ignored if AutoNegotiation is enabled (bit 12 of PR0 = 1). Collision test control. 1: collision test is enabled. 0: normal operation This bit, when set, causes the COL signal to be asserted as a result of the assertion of TX _EN within 512 BT. De-assertion of TX_EN will cause the COL signal to be de-asserted within 4BT. Reserved 0 R/W 14 13 XLBEN SPSEL 0 0 R/W R/W 12 ANEN 1 R/W 11 PDEN 0 R/W 10 ISOEN 0 R/W 9 RSAN 0 R/W 8 DPSEL 0 R/W 7 COLEN 0 R/W 6~0 --- 0 RO R/W = Read/Write able. RO = Read Only. 12/36 STE400P Table 3. Register Descriptions Bit # Name Descriptions Default Val RW Type PR1, MII Status Register. All the bits of this register are read only. 15 14 13 12 11 10~7 6 T4 TXFD TXHD 10FD 10HD --MFPS 100BASE-T4 ability. Always 0, since STE400P has no T4 ability. 100BASE-TX full duplex ability. Always 1, since STE400P has the 100BASE-TX full duplex ability. 100BASE-TX half duplex ability. Always 1, since STE400P has the 100BASE-TX half duplex ability. 10BASE-T full duplex ability. Always 1, since STE400P has 10Base-T full duplex ability. 10BASE-T half duplex ability. Always 1, since STE400P has 10Base-T half duplex ability. Reserved MF Preamble Suppression 0 = Will not accept management frames with preamble suppressed. A minimum of 32 preamble bits are required following power-on or hardware reset. One IDLE bit is required between any two management transactions as per IEEE 802.3u specification. 1 =Accepts management frames with preamble suppressed. Auto-Negotiation Completed. 0: Auto-Negotiation process is not completed. 1: Auto-Negotiation process is completed. Result of remote fault detection. 0: No remote fault condition detected. 1: Remote fault condition detected. This bit is set when the Link Partner transmits a remote fault condition (PR5 bit 13 = 1). Auto-Negotiation ability. Always 1, since STE400P has the Auto-Negotiation ability. Link status. 0: a failure link condition occurred. Read to set. 1: a valid link is established. Jabber detection. 1: jabber condition is detected (10Base-T only). Extended register supporting. Always 1, since STE400P supports extended register 0 1 1 1 1 0 0 RO RO RO RO RO RO R/W 5 ANC 0 RO 4 RF 0 RO/LH* 3 2 AN LINK 1 0 RO RO/LL* 1 0 JAB EXT 0 1 RO/LH* RO LL* = Latching Low and clear by read. LH* = Latching High and clear by read. PR2- PID HI, PHY Identifier(HI) 15~0 PHYID1 Pls. see NOTE on next page 1C04h RO PR3- PID LO, PHY Identifier (LO) 15~10 PHYID2 Please see NOTE on next page 000000b RO 13/36 STE400P Table 3. Register Descriptions Bit # 9~4 3~0 Name MODEL REV Descriptions Model number of STE400P. Six bits manufacture's model number. Revision number of STE400P. Four bits manufacture's revision number. Default Val 000010b 0001b RW Type RO RO NOTE: ST-OUI = {PHYID1[1:0], PHYID2[15:12], PHYID1[9:8], PHYID1[7:2], PHYID1[10:9], PHYID1[15:10]} This translates to ST OUI of : 00-80-E1 PR4- ANA, Auto-Negotiation Advertisement 15 NXTPG Next Page ability. 0: does not provide next page ability. 1: does provide next page ability. Reserved Remote Fault function. 1: with remote fault function. Reserved Flow Control function Ability. 1:supports PAUSE operation of flow control for full duplex link. 100BASE-T4 Ability. Always 0: since STE400P doesn't have 100BASE-T4 ability. 100BASE-TX Full duplex Ability. 1: with 100Base-TX full duplex ability. 100BASE-TX Half duplex Ability. 1: with 100Base-TX ability. 10BASE-T Full duplex Ability. 1: with 10Base-T full duplex ability. 10BASE-T Half duplex Ability. 1: with 10Base-T ability. Select field. Default 00001=IEEE 802.3 0 0 1 1 1 1 00001 R/W RO R/W R/W R/W R/W RO 0 R/W 0 R/W 14 13 12,11 10 9 8 7 6 5 4~0 --RF --FC T4 TXF TXH 10F 10H SF PR5- ANLP, Auto-Negotiation Link Partner ability 15 LPNP Link partner Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. Received Link Partner Acknowledge. 0: link code work had not received yet. 1: link partner successfully received STE400P's Link Code Word. Link Partner's Remote fault status. 0: no remote fault detected. 1: remote fault detected. Reserved 0 RO 14 LPACK 0 RO 13 LPRF 0 RO 12,11 --- 0 RO 14/36 STE400P Table 3. Register Descriptions Bit # 10 Name LPFC Descriptions Link Partner's Flow control ability. 0: link partner without PAUSE function ability. 1: link partner with PAUSE function full duplex link ability. Link Partner's 100BASE-T4 ability. 0: link partner without 100BASE-T4 ability. 1: link partner with 100BASE-T4 ability. Link Partner's 100BASE-TX Full duplex ability. 0: link partner without 100BASE-TX full duplex ability. 1: link partner with 100BASE-TX full duplex ability. Link Partner's 100BASE-TX Half duplex ability. 0: link partner without 100BASE-TX. 1: link partner with 100BASE-TX ability. Link Partner's 10BASE-T Full Duplex ability. 0: link partner without 10BASE-T full duplex ability. 1: link partner with 10BASE-T full duplex ability. Link Partner's 10BASE-T Half Duplex ability. 0: link partner without 10BASE-T ability. 1: link partner with 10BASE-T ability. Link partner select field. Default 00001=IEEE 802.3. Default Val 0 RW Type RO 9 LPT4 0 RO 8 LPTXF 0 RO 7 LPTXH 0 RO 6 LP10F 0 RO 5 LP10H 0 RO 4~0 LPSF 00000b RO PR6- ANE, Auto-Negotiation expansion 15~5 4 --PDF Reserved Parallel detection fault. 0: no fault detected. 1: a fault detected via parallel detection function. Link Partner's Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE400P's next Page ability. 0: without next page ability. 1: with next page ability. Page Received. 0: no new page has been received. 1: a new page has been received. Link Partner Auto-Negotiation ability. 0: link partner has no Auto-Negotiation ability. 1: link partner has Auto-Negotiation ability. 0 0 RO RO/LH* 3 LPNP 0 RO 2 NP 1 RO 1 PR 0 RO/LH* 0 LPAN 0 RO LH = High Latching and cleared by reading. PR7- NEXT PAGE, Auto-Negotiation Next Page Transmit Register 15 14 13 Next Page --Message Page 0: Last Page. 1: Additional Next Page or pages will follow. Reserved 0: Unformatted Page. 1: Message page. 0 0 1 R/W RO R/W 15/36 STE400P Table 3. Register Descriptions Bit # 12 Name ACK 2 Descriptions Acknowledge 2 0: Cannot Comply with message 1: Will Comply with message 0: Previous value of the transmitted Link Code Word = 0 1: Previous value of the transmitted Link Code Word = 1 Message / Unformatted Code Field Default Val 0 RW Type R/W 11 10~0 Toggle Message 0 1 RO R/W PR8- LP NXT PG, Auto-Negotiation Link Partner Next Page Transmit Register 15 14 13 12 Next Page --Message Page ACK 2 0: Last Page. 1: Additional Next Page(s) will follow. Reserved 0: Unformatted Page. 1: Message page. Acknowledge 2 0: Cannot Comply with message 1: Will Comply with message 0: Previous value of the transmitted Link Code Word = 0 1: Previous value of the transmitted Link Code Word = 1 Message / Unformatted Code Field 0 0 0 0 RO RO RO RO 11 10~0 Toggle Message 0 0 RO RO PR9- 100AUXCTL, 100BASE-X Auxiliary Control Register 15,14 13 12,11 10 --DISTX --DIS4B5B Reserved. Write as 0; Ignore on Read 1: Disable the Transmitter in the PHY. 0: Normal operation Reserved. Write as 0; Ignore on Read Enable 4B/5B encoder and decoder 1: the 4B/5B encoder and decoder are bypassed 0: the 4B/5B encoder and decoder are enabled.. Disable Scramble. 1: the scrambler and de-scrambler are disabled. 0: the scrambler and de-scrambler is enabled. Enable the conversions between NRZ and NRZI. 1: disable the data conversion between NRZ and NRZI. 0: enable the data conversion of NRZI to NRZ in receiving and NRZ to NRZI in transmitting. Reserved. Ignore on Read 00 0 00 0 R/W R/W 9 DISCRM 0 R/W 8 DISNRZI 0 R/W 7~0 --- 00000000 PR10- 100 AUX SR, 100BaseX Auxiliary Status Register 15~10 9 --Locked Reserved 1: descrambler locked 0: descrambler unlocked 0 0 RO RO 16/36 STE400P Table 3. Register Descriptions Bit # 8 Name 100 LS Descriptions Current 100BaseX link status 1: link pass 0: link fail Reserved FCD BAD ESD RED TED LCKED MLT3CED 1: False Carrier Detected since last read 0: no False Carrier since last read 1: ESD error detected since last read 0: no ESD error since last read 1: Receive Error Detected since last read 0: no Receive Error since last read 1: Transmit Error Detected since last read 0: no Transmit Error code received since last read 1: Lock Error Detected since last read 0: no Lock Error since last read 1: MLT3 Code Error Detected since last read 0: no MLT3 Code Error since last read 0 0 0 0 0 0 RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH Default Val 0 RW Type RO 7~6 5 4 3 2 1 0 PR11- 100 RX EC, 100BaseX Receiver Error Counter 15~8 7~0 Reserved REC Write as "00h"; Ignore when Read Number of Non-collision packets with Receive Errors since last Read 00h 00h RO RO PR12- 100 FCSC, 100BaseX False Carrier Sense Counter 15~8 7~0 Reserved FCSC Write as "00h"; Ignore when Read Number of False Carrier Sense events since last read 00h 00h RO RO PR13- AUX CSR, Auxiliary Control/Status Register 15 14 13~8 7~6 JD LD Reserved HSQ:LSQ 1=Jabber function disabled in PHY 0=Jabber function enabled in PHY 1=Link Integrity test disabled in PHY 0=Link Integrity test enabled in PHY Ignore when Read These two bits define the Squelch Mode of the 10Base-T Carrier Sense mechanism: 00=Normal squelch 01=Low squelch 10=Highl squelch 11=not allowed Ignore when Read 1=Auto Negotiation activated 0=Speed forced manually 0 0 000000 00 R/W R/W RO R/W 5~4 3 Reserved ANI 00 1 RO RO 17/36 STE400P Table 3. Register Descriptions Bit # 2 Name FI (100/10) Descriptions Force Indication 1=Speed forced to 100Base-X 0=Speed forced to 10Base-T Speed Indication 1=100Base-X 0=10Base-T Full Duplex Indication 1=Full-duplex active 0=Full-duplex not active Default Val 0 RW Type RO 1 SI 0 RO 0 FDI 0 RO PR14- AUX SSR, Auxiliary Status Summary Register 15 14 13 12 11 10~8 ANC ANFLGC ANAD ANABD ANP AN HCD 1=Auto Negotiation process completed 1=Auto Negotiation FLP-Link Good Check 1=Auto Negotiation acknowledge detected 1=Auto Negotiation for link partner ability STE400P and link partner Pause Operation bit set 000=NO Highest Common Denominator 001=10Base-T 010=10Base-T Full-duplex 011=100Base-TX 100=100Base-T4 101=100Base-TX Full-duplex 11x= undefined 1=Parallel Detection fault Link Partner Remote Fault 1=New page has been received 1=Link Partner is Auto-Negotiation capable Speed Indicator 1=100 Mbps 0=10 Mbps Link Status 1=Link is up (link pass state) 1=Auto Negotiation Enabled 1=Jabber condition detected 0 0 0 0 0 0 0 0 000 RO RO LH RO LH RO LH RO RO 7 6 5 4 3 ANPDF LPRF LPPR LPANA SI 0 RO LH RO RO LH RO RO 2 1 0 LS ANE JD 0 1 0 RO LL RO RO LL PR15- INT, Interrupt Register 15 FDX LED E Full Duplex LED Enable 0 R/W 18/36 STE400P Table 3. Register Descriptions Bit # 14 13 12 11 10 9 8 7~5 4 3 2 1 0 Name INTR E --NP Mask FDX Mask SPD Mask LK Mask INTR Mask Reserved NP_LP FDX C SPD C LNK C INTR S Link-partner's next-page received Duplex Change Interrupt Speed Change Interrupt Link Change Interrupt Interrupt Status 0 0 0 0 Interrupt Enable Reserved Next-Page Interrupt Mask Full-duplex Interrupt Mask SPEED Interrupt Mask Link Interrupt Mask Master Interrupt Mask Descriptions Default Val 0 0 1 1 1 1 1 0 RW Type R/W RO R/W R/W R/W R/W R/W RO RO LH RO LH RO LH RO LH RO LH PR16- AUX M2, Auxiliary Mode 2 Register 15~8 7 6 5 4 3 2~0 Reserved Ignore when Read FFh 0 0 0 0 0 000 RO R/W R/W R/W R/W R/W RO BEM 1=10Base-T half duplex TXEN won't echo onto RXDV (10Base-T) 0=10Base-T half duplex TXEN will echo onto RXDV TM LED A LED FO S LED SQE D Reserved 1=Traffic Meter LED Mode On 0=Traffic Meter LED Mode Off 1=Activity LEDs Forced On 0=Activity LEDs not Forced 1=Serial LED Mode enabled 0=Serial LED Mode disabled 1=SQE not transmitted in 10Base-T half-duplex 0=SQE transmitted in 10Base-T half-duplex Ignore when Read PR17- AUX EGSR 10Base-T Auxiliary Error and General Status Register 15~10 9 8 7~5 Reserved EOF error PI Revision Ignore when Read 1=EOF detection error 1=Channel Polarity Inverted Revision Number 000 0 0 001 RO RO RO RO 19/36 STE400P Table 3. Register Descriptions Bit # 4 3 2 Name Reserved ANI FI (100/10) Ignore when read 1=Auto-Negotiation activated 0=Speed forced manually Force Indication 1=Speed forced to 100Base-X 0=Speed forced to 10Base-T Speed Indication 1=100Base-X 0=10Base-T Full-duplex Indication 1=Full-duplex active 0=Full-duplex not active Descriptions Default Val 0 1 0 RW Type RO RO RO 1 SI 0 RO 0 FDI 0 RO PR18- AUX MODE, Auxiliary Mode Register 15~5 4 3 2 1 0 Reserved A LED FI L LED FI Reserved B TXEN Reserved 1=Enable Block TXEN mode Write as "00h"; Ignore when Read 1=Disable XMT/RCV Activity LED outputs 0=Allow XMT/RCV Activity LED outputs 1=Disable Link LED output 0=Allow Link LED output 000h 0 0 0 0 0 RO R/W RO R/W PR19- AUX MPR, Auxiliary Multiple PHY Register 15 14 13 12 11 10~9 8 7 6 5 4 HCD_TX_ FDX HCD_T4 HCD_TX 1=Auto Negotiation result is 100Base-TX full-duplex 0=STE400P doesn't support 100Base-T4 ability 1=Auto Negotiation result is 100Base-TX 0 0 0 0 0 0 0 0 0 0 0 RO RO RO RO RO RO R/W (SC) RO RO RO RO HCD_FDX 1=Auto Negotiation result is 10Base-T full-duplex (10Base-T) HCD 1=Auto Negotiation result is 10Base-T (10Base-T) Reserved R AN ANC FLP_L_GC AckD AD Ignore when Read 1=re-start Auto Negotiation process 0=no effect 1=Auto Negotiation process Completed 0=Auto Negotiation process not Completed 1=Auto Negotiation FLP-Link-Good-Check 1=Auto Negotiation Acknowledge Detected 1=Auto Negotiation waiting for LP Ability 20/36 STE400P Table 3. Register Descriptions Bit # 3 2~1 0 Name SI Reserved RXER C 1=Super Isolate Mode 0=Normal Operation Write as "00"; Ignore when Read 1=Enable RXER Code Mode 0=Disable RXER Code Mode Descriptions Default Val 0 00 0 RW Type R/W R/W R/W SC = Self Clear 7 DEVICE OPERATION The STE400P integrates the IEEE802.3u compliant functions of PCS(physical coding sub-layer), PMA(physical medium attachment) sub-layer, and PMD(physical medium dependent) sub-layer for 100BASE-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10BASE-T. All the functions and operation schemes are described in the following sections. 7.1 100BASE-TX TRANSMIT OPERATION Regarding the 100BASE-TX transmission, the device provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles to five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer with the turns ratio of 1: 1. Data code-groups Encoder: In normal MII mode application, the device receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the device on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE-TX. Idle code-groups: In order to establish and maintain the clock synchronization, the device needs to keep transmitting signals to the medium. The device will generate Idle code-groups for transmission when there is no real data want to be sent by MAC. Start-of-Stream Delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles are MAC preamble. In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the device will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups. End-of-Stream Delimiter-ESD (/T/R/): In order to indicate the termination of the normal data transmissions, the device will insert 2 nibbles of /T/R/ code-group after the last nibble of FCS. Scrambling: All the encoded data(including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce the EMI and spread the power spectrum using a 10-bit scrambler seed loaded at the beginning. Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmission data with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial function. After serialized, the transmission serial bit stream will be further converted from NRZ to NRZI format. This NRZI conversion function can be bypassed, if the bit 7 of PR19 register is cleared as 0. After NRZI converted, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. With this MLT3 code, it lowers the frequency and reduces the energy of the transmission signal in the UTP cable and also makes the system easily to meet the FCC specification of EMI. Wave-Shaper and Media Signal Driver: In order to reduce the energy of the harmonic frequency of transmission signals, the device provides the wave-shaper prior to the line driver to smooth but keep symmetric the rising/falling edge of transmission signals. The wave-shaped signals include the 100BASE-TX and 10BASE-T both are passed to the same media signal driver. This design can simplify the external magnetic connection with single one. 21/36 STE400P 7.2 100BASE-TX RECEIVING OPERATION Regarding the 100BASE-TX receiving operation, the device provides the receiving functions of PMD, PMA, and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns ratio of 1: 1. It includes the adaptive equalizer and baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B. Adaptive Equalizer and Baseline Wander: Since the high speed signals over the unshielded (or shielded) twisted Pair cable will induce the amplitude attenuation and phase shifting. Furthermore, these effects are depends on the signal frequency, cable type, cable length and the connectors of the cabling. So a reliable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to perform these functions. MLT3 to NRZI Decoder and PLL for Data Recovery: After receiving the proper MLT3 signals, the device converts the MLT3 to NRZI code for further processing. After adaptive equalizer, baseline wander, and MLT3 to NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the Phase Lock Loop circuits to extract out the original data and synchronous clock. Data Conversions of NRZI to NRZ and Serial to Parallel: After data is recovered, the signals will be passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion can be bypassed, if the bit 7 of PR19 register is cleared as 0. De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their original MII nibble type data. Carrier sensing: Carrier Sense(CRS) signal is asserted when the STE400P detects any 2 non-contiguous zeros within any 10 bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive. But in full duplex mode, CRS is asserted only during packet reception. 7.3 10BASE-T TRANSMISSION OPERATION This includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber function and the transmit wave-shaper and line driver described in the section of "Wave-Shaper and Media Signal Driver" of "100BASE-T Transmission Operation". It also provides Collision detection and SQE test for half duplex application. 7.4 10BASE-T RECEIVE OPERATION This includes the carrier sense function, receiving filter, PLL for clock and data recovering, Manchester decoder, and serial to parallel converter. 7.5 LOOP-BACK OPERATION The STE400P provides internal loop-back option for both the 100BASE-TX and 10BASE-T operations. Setting bit 14 of PR0 register to 1 can enable the loop-back option. In this loop-back operation, the TX and RX lines are isolated from the media. The STE400P also provides remote loop-back operation for 100BASE-TX operation. Setting bit 9 of PR19 register to 1 enables the remote loop-back operation. In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of NRZ to NRZI converter then loop-back to the receive path into the input of NRZI to NRZ converter. In the 100BASE-TX remote loop-back operation, the data is received from RX pins through receive path to the output of data and clock recover and then loop-back to the input of NRZI to MLT3 converter of transmit path then transmit out to the medium via the transmit line drivers. In the 10BASE-T loop-back operation, the data is through transmit path and loop-back from the output of the Manchester encoder into the input of Phase Lock Loop circuit of receive path. 22/36 STE400P 7.6 FULL DUPLEX AND HALF DUPLEX OPERATION The STE400P can operate for either full duplex or half duplex network application. In full duplex, both transmit and receive can be operated simultaneously. Under full duplex mode, collision(COL) signal is ignored and carrier sense(CRS) signal is asserted only when the STE400P is receiving. In half duplex mode, either transmit or receive can be operated at one time. Under half duplex mode, collision signal is asserted when transmit and receive signals collided and carrier sense asserted during transmission and reception. 7.7 AUTO-NEGOTIATION OPERATION The Auto-Negotiation function is designed to provide the means to exchange information between the STE400P and the network partner to automatically configure both to take maximum advantage of their abilities, and both are setup accordingly. The Auto-Negotiation function can be controlled through ANE, bit 12 of the PR0 register. Auto-Negotiation exchanges information with the network partner using the Fast Link Pulses(FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the burst pulses to advertise all remote partner's capabilities which are determined by the register of PR4. According to this information they find out their highest common capability by following the priority sequence as below: 1. 100BASE-TX full duplex 2. 100BASE-TX half duplex 3. 10BASE-T full duplex 4. 10BASE-T half duplex During power-up or reset, if Auto-Negotiation is found enabled then FLPs will be transmitted and the Auto-Negotiation function will proceed. Otherwise, the Auto-Negotiation will not occur until the bit 12 of PR0 register is set to 1. When Auto-Negotiation is disabled, then the Network Speed and Duplex Mode are selected by programming PR0 register. 7.8 POWER DOWN OPERATION To reduce the power consumption, the STE400P is designed with a power down feature, which can save the power consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separated, the STE400P can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other one of them is operating. There is also a Power Down mode which can be selected by PDEN in register PR0 bit 11. During the Power Down mode, TXP/TXN outputs and all LED outputs are 3-stated, and the MII interface is isolated. During Power Down mode the MII management interface is still available for reading and writing device registers. Power Down mode can be exited by clearing bit 11 of register PR0 or by a hardware or software reset (setting PR0:15=1). 7.9 LED DISPLAY OPERATION The STE400P provides 2 functions for the LED pins, the detail descriptions about the operation are described in the PIN Description section, and as follows. 7.10 RESET OPERATION There are two ways to reset the STE400P. First, for hardware reset, the STE400P can be reset via RESET pin (pin 119). The active low Reset input signal is required at least 1 ms to ensure proper reset operation. Second, for software reset, when bit 15 of register PR0 is set to 1, the STE400P will reset entire circuits and registers to their default values, and clear the bit 15 of PR0 to 0. Both hardware and software reset operations initialize all registers to their default values. This process includes re-evaluation of all hardware-configurable registers. Logic levels on several I/O pins are detected during hardware reset period to determine the initial functionality of STE400P. Some of these pins are used as outputs after the reset operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated configuration pins can be tied to the Vcc or ground directly. Configuration pins multiplexed with LED outputs should be weakly pulled up or weakly 23/36 STE400P pulled down through resistors as shown in the following circuits. Vcc I/O PIN 10k 10k I/O PIN Logic Level 1 Logic Level 0 7.11 PREAMBLE SUPPRESSION Preamble suppression mode in the STE400P is indicated by a one in bit six of the PR1 Register. If it is determined that all PHY devices in the system support preamble suppression, then a preamble is not necessary for each management transaction. The first transaction following power-up/hardware reset requires 32 bits of preamble. The full 32 bit preamble is not required for each additional transaction. The STE400P will respond to management accesses without preamble, but a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u. 7.12 REMOTE FAULT The remote fault function indicates to a link partner that a fault condition has occurred by using the Remote Fault bit, which is encoded in bit 13 of the Link Code Word. A local device indicates to its link partner that it has found a fault by setting the Remote Fault bit in the Auto-Negotiation register to logic one and renegotiating with the link partner. The Remote Fault bit remains at logic one until successful negotiation with the Link Code Word occurs. The bit will then return to 0. When the message is sent that the Remote Fault bit is set to logic one, the device will set the Remote Fault bit in the MII to logic one if the management function is present. 7.13 TRANSMIT ISOLATION STA/STE Ethernet ttp 1 PORT OF STE400P STEPHY1 RxD TxD 4/5 4/5 tpn MII TX(100MHz)/TP(10MHz) 24/36 STE400P 8 ELECTRICAL SPECIFICATIONS AND TIMINGS Table 4. Absolute Maximum Ratings Parameter Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection -0.5 V to 5.5 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -65 C to 150 C(-85F to 302F) 0C to 70C(32F to 158F) 2000V Value Table 5. General DC Specifications Symbol General DC Vcc Supply Voltage 3.15 3.3 3.45 V Parameter Test Condition Min. Typ. Max. Units 10BASE-T Voltage/Current Characteristics Vida10 Vidr10 Vod10 Icc10 Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Output Differential Peak Voltage Supply Current 100% utilization, min. IPG, Vcc=3.3V, including TX output driver 5MHz ~ 10MHz 5MHz ~ 10MHz 585 0 2200 270 3100 585 2800 mV mV V mA 100BASE-TX Voltage/Current Characteristics Vida100 Vidr100 Vod100 Icc100 Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Output Differential Peak Voltage Supply Current 100% utilization, min. IPG, Vcc=3.3V, including TX output driver 200 0 950 390 1000 200 1050 mV mV V mA 25/36 STE400P Table 6. AC Specifications Symbol X1 Specifications TX1d TX1p TX1t X1 Duty Cycle X1 Period X1 Tolerance 45 50 30 55 % ns PPM Parameter Test Condition Min. Typ. Max. Units 10BASE-T Normal Link Pulse(NLP) Timings Specifications TNPW TNPC NLP Width NLP Period 10Mbps 10Mbps 8 100 24 ns ms Figure 2. Normal Link Pulse timings Tnpw Tnpc Table 7. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units Auto-Negotiation Fast Link Pulse(FLP) Timings Specifications Tflpw Tflcpp Tflcpd Tflbw Tflbp FLP Width Clock pulse to clock pulse period Clock pulse to Data pulse period Number of pulses in one burst Burst Width FLP Burst period 8 111 55.5 17 2 16 24 100 125 62.5 139 69.5 33 ns s s pulse ms ms 26/36 STE400P Figure 3. Fast Link Pulse timing Tflcpp Tflcpd Tflpw Tflbw Tflbp Table 7. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units 100BASE-TX Transmitter AC Timings Specification Tjit TDP-TDN Differential Output Peak Jitter 1.4 ps MII Management Clock Timing Specifications t1 t2 t3 t4 t5 t6 MDC Low Pulse Width MDC High Pulse Width MDC Period MDIO(I) Setup to MDC Rising Edge MDIO(O) Hold Time from MDC Rising Edge MDIO(O) Valid from MDC Rising Edge 200 200 400 10 10 0 -- -- -- -- -- 300 ns ns ns ns ns ns 27/36 STE400P Figure 4. MII Management Clock Timing t1 MDC t4 MDIO(I) t6 MDIO(O) t5 t2 t3 Table 7. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units MII Receive Timing Specification t1 t2 t3 RX-ER, RX-DV, RXD[3:0] Setup to RX-CLK RX-ER, RX-DV, RXD[3:0] Hold After RX-CLK RX-CLK High Pulse Width (100 Mbits/s) RX-CLK High Pulse Width (10 Mbits/s) t4 RX-CLK Low Pulse Width (100 Mbits/s) RX-CLK Low Pulse Width (10 Mbits/s) t5 RX-CLK Period (100 Mbits/s) RX-CLK Period (10 Mbits/s) 14 140 40 400 10 10 14 200 26 260 -- -- 26 ns ns ns ns ns ns ns ns 28/36 STE400P Figure 5. MII Receive Timing Table 7. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units MII Transmit Timing Specification t1 t2 TX-ER,TX-EN,TXD[3:0] Setup to TX-CLK Rise TX-ER,TX-EN,TXD[3:0] Hold After TX-CLK Rise 10 0 -- 25 ns ns Figure 6. MII Transmit Timing 29/36 STE400P Table 7. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units Receive Timing Specification Rt1 Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt2 Receive Frame to CRS High (100Mbits/s) Receive Frame to CRS High (10 Mbits/s) Rt3 End of Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) End Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt4 End of Receive Frame to CRS Low (100 Mbits/s) End of Receive Frame to CRS Low (10 Mbits/s) -- 15 bits -- 22 bits -- -- -- 13 5 12 Bits bits bits -- 13 -- 4 24 4.5 bits bits bits Figure 7. Receive Timing 30/36 STE400P Table 7. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units Transmit Timing Specification t1 TX-EN Sampled to CRS High (100 Mbits/s) TX-EN Sampled to CRS High (10 Mbits/s) t2 TX-EN Sampled to CRS Low (100 Mbits/s) TX-EN Sampled to CRS Low (10 Mbits/s) t3 Transmit Latency (100 Mbits/s) Transmit Latency (10 Mbits/s) t4 Sampled TX-EN Inactive to End of Frame (100 Mbits/s) Sampled TX-EN Inactive to End of Frame (10 Mbits/s) 0 -- 0 -- 6 4 -- 4 1.5 16 16 14 -- 17 bits bits bits bits bits bits bits -- 5 bits Figure 8. Transmit Timing 31/36 STE400P Figure: 11 Transmit Timing TXP Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency) Sym t2A t2B t2C t2D t2E Min 10 5 6 Typ 3 4 10 Max 4 16 14 Units ns ns BT BT BT BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 32/36 STE400P 33/36 STE400P Figure 12: 10Base-T Transmit Timing TXP Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency) Sym t8A t8B t8C t8D t8E Min 10 5 - Typ 0 8 3-5 Max 4 Units ns ns BT BT BT BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 34/36 STE400P 9.0 PACKAGE 35/36 STE400P PACKAGE TYPE: PQFP 208 / BODY 28X28X3.49mm Dimensions mm REF A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.25 3.40 0.17 0.09 30.60 28.00 25.50 0.50 30.60 28.00 25.50 0.60 1.30 0.75 0.018 3.20 3.60 0.27 0.20 Dimensions inch MIN. TYP. MAX 0.161 0.010 0.134 0.007 0.003 1.205 1.102 1.004 0.020 1.205 1.102 1.004 0.024 0.51 0.029 0.126 0.142 0.011 0.008 MIN. TYP. MAX. 4.10 0 deg. (min), 3.5 deg. (typ.), 7 deg.(max) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 36/36 |
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